Embedded Processor Watch

Editor: Jim Turley
Sr. Editor: Tom Halfhill

In This Issue:

• Special Forum Issue!
• Intel Unveils StrongARM-2 at Embedded Processor Forum
• QED Announces First Embedded Copper Processor
• Industry Resources: A MIPS Book for Every Tom, Dick, and Harry
• Industry Resources: A Stanford Education on the Cheap
• New Embedded IC Announcements

Special Forum Issue!

This issue of Embedded Processor Watch is coming directly from the Embedded Processor Forum in San Jose, and includes "live" coverage of announcements made this morning.

Intel Unveils StrongARM-2 at Embedded Processor Forum

This morning at the Embedded Processor Forum, Intel design manager Jay Heeb lifted the veil on StrongARM-2, revealing the alluring outline of a new pipeline, a process shift, and some design tradeoffs that increase frequency dramatically. He also reiterated Intel's plan to produce both standalone microprocessors (ala the SA-110) and integrated devices (like the recently announced SA-1110; see Embedded Processor Watch #42). The second-generation StrongARM (Intel avoids calling it StrongARM-2) should reach 600 MHz in early 2000 while still staying below the self-imposed 500-mW barrier. As with the original StrongARM, the SA-2 should lead the industry in MIPS/Watt.

Intel's three major goals were to preserve StrongARM's lead in performance, keep power consumption below 500 mW, and make SA-2 manufacturable on standard Intel processes. To maintain a speed lead, Intel had four years of catching up to do.

The usual course of action in such cases is to lengthen the pipeline, and this Intel did. Early ARM chips have a constipated three-stage pipeline with a heavily burdened final stage. The first StrongARM (see Microprocessor Report 11/13/95, p. 16) opened up the pipeline to five stages, rectifying some congestion. Rather than disembowel this arrangement completely, Intel simply eliminated a few of the remaining pinch points.

The first clutch of SA-2 processors will be built in a new 0.18-micron CMOS process. Like hemophilia, StrongARM will skip a generation, moving from 0.35 micron directly to 0.18 micron, passing over the 0.25-micron generation entirely. The unnamed 0.18-micron process is closely related to Intel's P858 (see Microprocessor Report 1/25/99, p. 22), the six- layer-metal process that clings to aluminum, not copper, interconnects.

The core voltage for the SA-2 will be variable between 0.75 V and 1.3 V. At the lowest voltage, the core should run at a respectable 150 MHz while drawing a mere 40 mW (including the core, caches, cache logic, and MMU, but no bus interfaces). At 1.3 V, Intel expects the SA-2 to hit a remarkable 600 MHz while still holding core power dissipation below 500 mW. There may be more. The P858 process is rated for 1.5-V operation, and the extra 200 mV may give cocky clock-speed cowboys a 100-MHz bonanza.

The contrasts between the SA-2 and the i960, Intel's other 32-bit embedded family, could not be more stark. The i960 survived on cast-off semiconductor processes, two to three generations old; the i960CA is still built in a 1.0-micron process (perhaps by little old ladies with Xacto knives). The original i960MX chip was so large its corners had to be rounded to fit within the reticle.

It will be nearly a year (1Q00) before Intel produces first silicon of SA-2, and at least a few additional months before general sampling begins. That's an unusually long warning period for Intel, and could have a chilling (Osborne-like) effect on SA-1 sales. More important, it will cloud competitors' brows and influence design decisions made from now until 1Q00. Until that time, SA-2 will cast a long shadow over low- power, high-performance competitors. When the clouds break and the chip arrives next year, it will usher in a new millennium for Intel's embedded strategy.

QED Announces First Embedded Copper Processor

At the Embedded Processor Forum, the denizens of QED, continuing a tradition of imminently practical if not profoundly ambitious CPU designs, rolled out their latest model for 2000. The RM7010 is an updated 64-bit MIPS core targeted for IBM's 0.18-micron copper process. QED expects first silicon of the RM7010 in early 2000, which could make it the first embedded processor ever to use copper.

At the microarchitectural level, the RM7010 changes almost not at all from the RM7000 (see Microprocessor Report 10/28/96, p. 6). It has the same dual-issue pipeline with no branch prediction, but it halves the on-chip level-2 cache to 128K. The cache excision was made because QED expects to use the RM7010 core in a range of highly integrated processors, not necessarily as a standalone CPU.

This strategy makes perfect sense; the RM7000 already addresses such market as exists for high-end 64-bit superscalar MIPS parts. Another standalone version with half the cache would be insufficiently differentiated to be worthwhile. On the other hand, the company's Alpine internal I/O structure (see Embedded Processor Watch #26) would make an ideal repository for an RM7010 brain. A hypothetical "Alpine II" product line with integrated PCI, network channels, and perhaps coprocessors would make a fine basis for set-top boxes, fast printers, and networking equipment.

Although the prospect of 0.18-micron copper processing is exciting, the RM7010's expected clock frequency is less so. During his presentation, QED founder Tom Riordan said he expects his latest brainchild to run at about 350 MHz--slow by the standards of a 1998-vintage Pentium II, never mind a chip due to come off IBM's preeminent process line in 2000. Part of the answer lies in the details of IBM's process: the CMOS-7SF process that QED is using has denser transistors than CMOS-7S (see Microprocessor Report 9/14/98, p. 1), but is not as fast.

Nevertheless, it appears QED's devotion to the relatively simple five- stage pipeline may be catching up with it. If the RM7010 can eke out only 350 MHz using one of the world's best fabrication technologies, it may be time for QED to get out its heavy pipefitting tools and get ready for some serious plumbing.

Industry Resources: A MIPS Book for Every Tom, Dick, and Harry

Morgan Kaufmann Publishers have released "See MIPS Run," a softcover book on the eponymous microprocessor. Written by British engineer Dominic Sweetman (don't worry; everything's spelled correctly), with a foreword by John Hennessy (the father of MIPS), this 475-page book is written primarily for embedded systems designers and programmers. Individual chapters are dedicated to cache, coprocessors, and control registers, interrupts and initialization, and C, assembly, and floating- point programming, with lots of code examples.

The book sells for $50 and is available on-line from the publishers at http://www.mkp.com/books_catalog/1-55860-410-3.asp or by writing to orders@mkp.com.

Industry Resources: A Stanford Education on the Cheap

The maroons at Leland Stanford, Jr. University are reigniting the 19th annual Western Institute of Computer Science (WICS) throughout July and August. The WICS program consists of more than a dozen different 2-day to 5-day courses for the career development of computer-industry professionals. Courses are held on the Stanford campus; selected courses are also available via the Internet or corporate intranets.

This year's offerings cover software testing, Web site design, human/computer interfaces, graphics and animation, object programming, Java, IS, C++, and voice over IP, among other topics.

The first classes begin July 12. Registration fees start at $1,450, with discounts for registering 30 days early, for attending in a group of five or more, or for being a WICS alumnus. For more information, or to register, contact Joleen Barnhill (Magalia, Calif.) at 530.873.0575, write barnhill@cs.stanford.edu, or visit http://wics.stanford.edu.

New Embedded IC Announcements

SK70740 (Level One) HDSL2 chip set provides analog front end, transceiver and FEC/frame, sub-rates down to 144 Kbps; in 64-pin QFP package. Price: $60.56/1,000; Production: Now; Call Level One at 916.855.5000.

CN8223 (Conexant) ATM physical interface provides 4-port parallel FIFO interface, access to ATM protocol at all levels; transmit/receive function to 155 Mbps. Price: $40/1,000; Samples: Now; Production: 2Q99; Call Conexant at 714.245.7500.

CN9419 (Conexant) Single-chip cable modem supports DOCSIS v1.1; includes 10-bit A/D converter, and a 40/56-bit encryption engine. Price: $45/10,000; Samples: Now; Production: 1Q00; Call Conexant at 714.245.7500.

CS61584A (Cirrus Logic) Dual line-interface unit for T1/E1 lines in PCM/voice-channel data banks and concentrators, T1/E1 multiplexers, digital access cross-connect systems. Price: $19/1,000; Production: Now; Call Cirrus at 510.249.4244.

DiskOnChip 2000 (M-Systems) Nonvolatile memory has 144-MByte capacity using flash memory mounted in a standard 32-pin DIP that can be socketed or soldered. Price: $347/10,000; Production: Now; Call M-Systems at 510.413.5950.