History of Marvell CPUs

Marvell's CPUs are among the most advanced embedded cores in the world in terms of high performance and low power consumption. Marvell CPUs are also compatible with ARM's instruction set, which is, the most popular embedded CPU architecture in the marketplace.

The evolution of the Marvell's CPU technology is linked to the proliferation of the ARM instruction set, which has become a de facto standard for embedded CPUs. The high performance and low power consumption of today's Marvell Sheeva CPUs also owe much to the significant micro-architectural features and improvements developed by a top-tier line up of processor developers.

The first ARM instruction set CPUs were designed for use in PCs, but the power-efficient design was quickly recognized as a breakthrough that could bring both high performance and low power requirements to the emerging market for handheld Personal Digital Assistant's (PDAs) such as Apple Computer's Newton.

Today, about 80 percent of all 32-bit embedded processors utilize the ARM instruction set. As the ARM architecture grew in popularity, companies such as Intel (XScale) and Marvell looked to improve upon the performance of ARM cores by obtaining ARM architectural licenses and developing their own ARM instruction set compliant CPUs.

Marvell utilizes the ARM architecture as a foundation for building its CPU cores, which feature a unique, high-performance, low-power Marvell micro-architecture. Today, with over 1,000 engineers dedicated to Sheeva CPU development, Marvell has the world's largest ARM-compatible CPU design team, delivering the most advanced embedded CPUs in the marketplace.

The Road to Sheeva

Marvell's Sheeva CPU has a rich heritage based on more than two decades of development work by pioneers in microprocessor development. The following timeline traces some of the milestones that paved the road for Marvell's Sheeva.

The 1980's - The first ARM processors

In 1985, Acorn Computers Ltd., a UK company, developed the ARM1 and ARM2 microprocessors. These are the first commercially available Reduced Instruction Set Computing (RISC) processors in the world. In 1989, Acorn released the ARM3, which improved the performance of the ARM2 with the addition of a 4KB cache.

In this period a debate raged among microprocessor designers over the advantages of Reduced Instruction Set Computing (RISC) architectures versus Complex Instruction Set Computing (CISC) architectures. While market leaders such as Intel promoted CISC, new challengers maintained that the RISC approach would ultimately displace CISC.

The 1990's

The ARM architecture and instruction sets were quickly adopted into the microcontroller, handheld device and consumer markets such as set top boxes.

In 1990, Acorn Computers spun off its microprocessor design team into a new company called Advanced RISC Machines Ltd (ARM). This lead to the development of the ARM6 core, used by Apple in its groundbreaking Newton Personal Digital Assistant (PDA).

1995

ARM introduced the ARM7TDMI core, utilizing the ARMv4T architecture. The 3 stage pipelined processor was delivered as a hard macrocell, designed to be embedded in System-on-a-Chip (SoC) solutions and optimized to provide the best combination of performance, power and size characteristics. This version of the ARM processor was widely and quickly adopted for use as a microcontroller and as the central processor in popular hand-held video game products.

Digital Equipment Corporation (DEC) and ARM collaborated to create a faster CPU than the existing ARM products. The result of their efforts was the StrongARM SA-110, a RISC chip intended for embedded systems. It featured separate instruction/data caches.

1998

Intel acquired StrongARM from DEC as part of a patent litigation settlement.

The 2000s

As the popularity of the ARM architecture grew beyond microcontrollers and handheld devices, companies such as Marvell acquired ARM architecture licenses to enable the development of micro-architectures with superior power and performance to open new market opportunities such as networking equipment and consumer electronics.

2000

Intel released the first XScale design, based partially on StrongARM. This stand alone CPU core, named the 80200, was a high-speed embedded processor compatible with the ARM v5 architecture.

2001

ARM introduced the ARM9 family of CPU cores, using the ARMv5TEJ architecture. These CPUs featured a 5 stage pipeline and enhanced digital signal processing support.

2002

Intel released the first XScale application processor, the PXA210 and PXA25X family.

2003

Marvell acquired an ARM architecture license, enabling the Company to develop its own ARM instruction set complaint CPU. That year Marvell launched its first ARMv5 Architecture-compliant Feroceon CPU. The CPU featured out-of-order execution and was optimized for extremely small size, low-power and high-performance

Marvell introduced Osprey (internal code name) into the Feroceon family. This single issue, out-of-order execution CPU included tightly coupled memory.

ARM launches the first cores in the ARM11 family, which utilized the ARMv6 architecture. These cores were designed for use as applications processors for consumer and wireless products

2004

The Marvell Feroceon family expanded with the introduction of Mohawk (internal code name), an extremely high-performance CPU featuring instruction and data caches, out-of-order execution, and full ARM compatibility.

The Intel XScale PXA27X family was released. These processors introduced Wireless MMX instructions for multimedia applications.

ARM announced Cortex M3, the first in a line of new Cortex family of processor cores.

2005

Marvell introduced Feroceon Dragonite (internal code name), an extremely small, low-powered CPU designed for microcontroller and storage applications.

Marvell reached a new milestone with the Feroceon Jolteon (internal code name) CPU core. Featuring a dual issue, superscalar, out-of-order execution engine, Jolteon CPUs are among the highest performing and most advanced embedded ARM instruction set compliant CPU cores in the world.

2006

Marvell acquired Intel's Application and Communication Processor (formerly known as Xscale), business unit. The combined engineering resources of Feroceon and Xscale give Marvell the world's largest CPU development team dedicated to ARM instruction set compatibility.

Following the acquisition of XScale, Marvell announced the release of the PXA30X family of processors.

2007

Marvell introduced the first CPU core developed by the joint engineering efforts of the Feroceon and former Xscale teams. This core pushed performance to the next level, featuring Wireless MMX2, floating point support, and compliance with both the ARMv5 and Intel XScale architectures.

2008

Marvell proudly launched Sheeva, an internally developed CPU technology. The first implementation of Sheeva set a new standard for embedded CPU performance. One of the most advanced CPUs in the world, the superscalar, dual issue, out-of-order execution Sheeva CPU runs at over 1 GHz. It contains advanced three-level branch prediction, a variable stage pipeline, and an integrated memory controller, providing unmatched high-end performance and low-power requirements. Compliant with the Cortex A8, Sheeva also supports both the ARMv6 and ARMv7 instruction sets, making it the world's first dual ARM ISA compatible CPU.

The first commercial product with the ARM Cortex A8 is released. Cortex A8 is ARM's first superscalar processor.

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